1、本科生课程  嵌入式系统概论、计算机组成与结构、计算机网络

2、研究生课程  嵌入式系统

3、研究生课程  嵌入式系统高级C语言编程

1、2018年国家教学成果二等奖 “适应现代微电子产业发展的本硕博贯通式创新人才培养模式的改革与实践” ，排名第10

2、2013年江苏省教学成果二等奖 “芯片和软件协同的嵌入式系统系列课程建设与实践”，排名第2

1、时龙兴，凌明，王学香. “嵌入式系统-基于SEP3203微处理器的应用开发”，电子工业出版社，2006.

2、凌明. “嵌入式系统高级C语言编程”，北京航空航天大学出版社，2011.

3、凌明，王学香，单伟伟. “嵌入式系统-从SoC芯片到系统”（第二版），电子工业出版社，2017.

4、钟锐，凌明，陈志坚. “基于玄铁802/803 微处理器内核的嵌入式系统设计”，学院出版社，2020

计算机体系结构及其量化分析、存储子系统、领域专用架构、嵌入式系统

1、国家自然科学基金委员会, 面上项目, 61974024, 宽电压时序推测型高速缓存（Cache）电路与架构优化研究, 2020-01-01 至 2023-12-31, 60万元, 在研, 主持

2、OPPO广东移动通信有限公司, 横向项目, 智能终端系统软硬一体创新技术联合研发中心, 2022-06 至 2025-06, 500万元, 在研, 主持

3、南京沁恒微电子股份有限公司, 横向项目, 学院-沁恒RISC-V内核微处理器技术联合研发中心, 2022-01 至 2024-12, 500万元, 在研, 主持

4、OPPO广东移动通信有限公司, 横向项目, Testbench 合成技术研究项目, 2022-03 至 2023-09,84.36万元, 在研, 主持

5、国家科技部, 国家项目, 2018YFB2202804, 基于超陡亚阈摆幅器件的 MCU 关键逻辑电路设计, 2019-08 至 2023-07, 200万元, 在研, 参与

6、江苏省农科院, 江苏省农业科技自主创新资金项目, CX(21)3121, 面向奶牛发情期预测的极低功耗耳标设计, 2021-06 至 2022-06, 20万元, 在研, 主持

7、江苏省科技厅, 江苏省自然科学基金, BK20181141, 面向移动计算的 多核 乱序处理器存储架构解析建模研究, 2018-07 至 2021-12, 10万元, 结题, 主持

8、江苏省科技厅, 江苏省重点研发计划项目, BE2018002-3, 面向ADAS的SoC芯片宽电压低功耗技术研发,2018-06 至 2021-09, 100万元, 结题, 参与

[1] Ming Ling; Qinde Lin; Ruiqi Chen; Haimeng Qi; Mengru Lin; Yanxiang Zhu; Jiansheng Wu ; Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and LowLevel Parallelism, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022

[2] Ming Ling, Q. Lin, K. Tan, T. Shao, S. Shen and J. Yang, A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 12, pp. 2197-2209, Dec. 2021, doi: 10.1109/TVLSI.2021.3120653.,

[3] S. Shen, P. Cao, M. Ling and L. Shi, A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/TCAD.2022.3194812.

[4] Tang, Shidi, Ruiqi Chen, Mengru Lin, Qingde Lin, Yanxiang Zhu, Ji Ding, Haifeng Hu, Ming Ling, and Jiansheng Wu. Accelerating autodock vina with gpus. Molecules 27, no. 9 (2022): 3041.

[5] Ming Ling, J. Ge, G. Wang, ”Fast modeling L2 cache reuse distance histograms using combined locality information from software traces,” Journal of Systems Architecture, Volume 108, 2020, 101745, ISSN 1383-7621 doi: 10.1016/j.sysarc.2020.101745.

[6] Shen, Shan, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling*, Jun Yang, and Longxing Shi. TS cache: A fast cache with timing-speculation mechanism under low supply voltages. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 1 (2019): 252-262.

[7] Chen, Ruiqi, Tianyu Wu, Yuchen Zheng, and Ming Ling*. MLoF: Machine Learning Accelerators for the Low-Cost FPGA Platforms. Applied Sciences 12, no. 1 (2022): 89.

[8] Ling, Ming, Hongxi Li, and Xiang Yu. A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools. IEEE Embedded Systems Letters (2021).

[9] Jin, Leilei, Wenjie Fu, Ming Ling*, and Longxing Shi. A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2021).

[10] Ling, Ming, Xiaoqian Lu, Guangmin Wang, and Jiancong Ge. Analytical modeling the multi-core shared cache behavior with considerations of data-sharing and coherence. IEEE Access 9 (2021): 17728-17743.

[11] Shen, Shan, Liang Pang, Tianxiang Shao, Ming Ling*, Xiao Shi, and Longxing Shi. TYMER: A yield-based performance model for timing-speculation SRAM. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2020.

[12] Fu, Wenjie, Leilei Jin, Ming Ling*, Yu Zheng, and Longxing Shi. A cross-layer power and timing evaluation method for wide voltage scaling. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2020.

[13] Shen, Shan, Tianxiang Shao, Ming Ling, Jun Yang, and Longxing Shi. Modeling and designing of a PVT auto-tracking timing-speculative SRAM. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1073-1078. IEEE, 2020.

[14] Wang, Guangmin, Jiancong Ge, Yunhao Yan, and Ming Ling*. A data-sharing aware and scalable cache miss rates model for multi-core processors with multi-level cache hierarchies. In 2019 IEEE 25th International Conference on Parallel and Distributed Systems (ICPADS), pp. 267-274. IEEE, 2019.

[15] Shang, Xiaojing, Ming Ling*, Shan Shen, Tianxiang Shao, and Jun Yang. RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. In Proceedings of the International Symposium on Memory Systems, pp. 451-458. 2019.

[16] Ling, Ming, Xin Xu, Yushen Gu, and Zhihua Pan. Does the ISA Really Matter? A Simulation Based Investigation. In 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 1-6. IEEE, 2019.

[17] Ling Yan, Yunhao, and Ming Ling. Accelerating the analytical modeling of memory level parallelism by the probability analysis. In 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 1-6. IEEE, 2019.,

[18] Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, and Jun Yang. Lowering the hit latencies of low voltage caches based on the cross-sensing timing speculation SRAM. IEEE Access 7 (2019): 111649-111661.

[19] Fu, Wenjie, Ming Ling*, Wei Wang, and Longxing Shi. Amps: Accelerating mcpat power evaluation without cycle-accurate simulations. IEEE Embedded Systems Letters 12, no. 1 (2019): 13-16.

[20] Ge, Jiancong, and Ming Ling. Fast modeling of the L2 cache reuse distance histograms from software traces. In 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 145-146. IEEE, 2019.

[21] Liu, Kaiyang, Jun Peng, Liang He, Jianping Pan, Shuo Li, Ming Ling, and Zhiwu Huang. An active mobile charging and data collection scheme for clustered sensor networks. IEEE Transactions on vehicular technology 68, no. 5 (2019): 5100-5113.

[22] Ling, Ming, Xiaojing Shang, Kecheng Ji, and Longxing Shi. Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations. Microprocessors and Microsystems 64 (2019): 159-169.

[23] Shen, Shan, Ming Ling, Yongtao Zhang, and Longxing Shi. RDV: A New Method for Memory Phase Detection and Simulation Points Selection. In 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM), pp. 374-379. IEEE, 2018.

[24] Shen, Shan, Ming Ling*, Yongtao Zhang, and Longxing Shi. Detecting the phase behavior on cache performance using the reuse distance vectors. Journal of Systems Architecture 90 (2018): 85-93.

[25] Ji, Kecheng, Ming Ling*, Longxing Shi, and Jianping Pan. An analytical cache performance evaluation framework for embedded out-of-order processors using software characteristics. ACM Transactions on Embedded Computing Systems (TECS) 17, no. 4 (2018): 1-25.

[26] Wang, Qin, Kecheng Ji, Ming Ling, and Longxing Shi. A mechanistic model of memory level parallelism fed with cache miss rates. In 2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 1-6. IEEE, 2017.

[27] Sun, Fengying, Kecheng Ji, Ming Ling, and Longxing Shi. A trace-driven analytical model with less profiling overhead for dram access latencies. In 2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 1-6. IEEE, 2017.

[28] Ji, Kecheng, Ming Ling, Qin Wang, Longxing Shi, and Jianping Pan. AFEC: An analytical framework for evaluating cache performance in out-of-order processors. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 55-60. IEEE, 2017.

[29] Ji, Kecheng, Ming Ling*, and Longxing Shi. Using the first-level cache stack distance histograms to predict multi-level LRU cache misses. Microprocessors and Microsystems 55 (2017): 55-69.

[30] Ji, Kecheng, Ming Ling*, Yang Zhang, and Longxing Shi. An artificial neural network model of LRU-cache misses on out-of-order embedded processors. Microprocessors and Microsystems 50 (2017): 66-79.